This invention relates to a semiconductor unit, a semiconductor module, and a memory system and, in particular, to a semiconductor unit, a semiconductor module, and a memory system where degradation of data signals or the like hardly occurs on high-speed operation.
Recent years, demand for high-speed becomes high more and more in a memory system. Specifically, in a high-speed memory system, performance coping with a high frequency such as hundreds of MHz through several GHz is required. In general, in the memory system, when a operation frequency becomes high, a waveform is easily confused on propagating of a signal on a wire. Accordingly, device is performed to a signal wiring so that a signal propagates accurately and a high-speed.
For example, United State Patent Application Publication No. US 2001/0024389 A1 discloses a memory system operable at a high-speed in which branches of the signal wiring are cut and reflection of a signal occurring in a branch of a wire is decreased. The memory system disclosed in United State Patent Application Publication No. US 2001/0024389 A1 will later be described in conjunction with FIG. 1. However, when the memory system further operates at the high-speed, problem arise in distortion of the signal waveform generated because the signal reflected at an end portion of an intra-package wire goes and returns the intra-package wire in the manner which will later become clear. In addition, in the memory system where the intra-package wire branches the signal path, there is a limit in a high-speed of the operating frequency.
Japanese Unexamined Patent Publication of Tokkai No. 2001-68617 or JP-A 2001-68617 describes a technique where a plurality of semiconductor elements are laminated in a memory module. In the technique described in JP-A 2001-68617, signal wires which are formed directly below the semiconductor elements, which connect an end of a substrate with another end thereof, and which extend in parallel with the substrate comprise as a line of wires. Signal wires which are formed in a laminating direction though via holes alternately disposed at the end and the other end of the substrate comprise as a line of wires. Such signal wires cope with at the high-speed operation. However, in JP-A 2001-68617, inasmuch as the signal wires extending in parallel with the substrate pass through directly below the semiconductor elements for a long section, problems arise where cross-talk noises (electromagnetic coupling noises) are superimposed from the signal wiring to signal wires within the semiconductor elements and power-supply wires when the operating frequency becomes the high-speed. In addition, problems arise where when laminating of the semiconductor elements are carried out, heat generated from the semiconductor elements concentrates, temperature of the module increases, and degradation of performance is caused.
In a memory module operating at a high-speed, it is necessary to carry out timing control of various signals arriving at a device at a high precision. In order to carry out the timing control at the high precision and to spread both of data wires and command address wires without problem from the point of view of timing error, signal reflection, cross-talk, and so on, an occupied area of the signal wires on the layout increases and degree of freedom of the wires decreases. Specifically, in the command address wires, it is necessary to distribute signals from resisters mounted on the memory module to all of the memory devices, by demands of miniaturization of the module, a large capacity of the memory chip, increase of the number of the command address wires caused by a function extension and so on, problems arise where the occupied area of the wiring further increases, the degree of freedom of the wiring decreases, and the layout is harsh moreover.
In addition, in the conventional memory module, by a restriction of a position relationship between terminals on the module substrate to be wired and terminals on the memory device corresponding thereto and by a restriction of an area which cannot wiring such as a resister IC for a command address signal disposed on the module substrate and a PLL (Phase-Locked Loop) IC for a clock buffer, a drawing of signal wires from terminals of the memory module to terminals of the memory device is complicated and a wiring length of the signal wires may increase. Inasmuch as the above-mentioned signal wires correspond to the branch wires in the memory system having blanches carrying out signal transmission at order of hundreds of MHz, problems arise where increase of the wiring length increases distortion of the signal waveform generated by reflecting and reciprocating of signals within the blanch wires.
EP 0818734 A2 discloses, as a memory system enable at a high-speed operation, an example of the memory system due to high-speed and small-signal-amplitude interface standard SSTL (stub series terminated logic), which was adopted by JEDEC (a lower branch of the Electronics Industries Association in the United States) as an industry standard. The memory system disclosed in EP 0818734 A2 will later be described in conjunction with FIG. 3.